Electrolytic Cu metallization is employed in the field of microelectronics manufacture to provide electrical interconnection in a wide variety of applications, such as, for example, in the manufacture of semiconductor integrated circuit (IC) devices. The demand for manufacturing semiconductor IC devices such as computer chips with high circuit speed and high packing density requires the downward scaling of feature sizes in ultra-large-scale integration (ULSI) and very-large-scale integration (VLSI) structures. The trend to smaller device sizes and increased circuit density requires decreasing the dimensions of interconnect features. An interconnect feature is a feature such as a via or trench formed in a dielectric substrate which is then filled with metal to yield an electrically conductive interconnect. Further decreases in interconnect size present challenges in metal filling.
Copper has been introduced to replace aluminum to form the connection lines and interconnects in semiconductor substrates. Copper has a lower resistivity than aluminum and the thickness of a Cu line for the same resistance can be thinner than that of an aluminum line.
The use of copper has introduced a number of requirements into the IC manufacturing process. First, copper has a tendency to diffuse into the semiconductor's junctions, thereby disturbing their electrical characteristics. To combat this occurrence, a barrier layer, such as titanium nitride, tantalum, tantalum nitride, or other layers as are known in the art, is applied to the dielectric prior to the copper layer's deposition. It is also necessary that the copper be deposited on the barrier layer cost-effectively while ensuring the requisite coverage thickness for carrying signals between the IC's devices. As the architecture of ICs continues to shrink, this requirement proves to be increasingly difficult to satisfy.
One conventional semiconductor manufacturing process is the copper damascene system. Specifically, this system begins by etching the circuit architecture into the substrate's dielectric material. The architecture is comprised of a combination of the aforementioned trenches and vias. Next, a barrier layer is laid over the dielectric to prevent diffusion of the subsequently applied copper layer into the substrate's junctions, followed by physical or chemical vapor deposition of a copper seed layer to provide electrical conductivity for a sequential electrochemical process. Copper to fill into the vias and trenches on substrates can be deposited by plating (such as electroless and electrolytic), sputtering, plasma vapor deposition (PVD), and chemical vapor deposition (CVD). It is generally recognized electrochemical deposition is the best method to apply Cu since it is more economical than other deposition methods and can flawlessly fill into the interconnect features (often called “bottom up” growth). After the copper layer has been deposited, excess copper is removed from the facial plane of the dielectric by chemical mechanical polishing, leaving copper in only the etched interconnect features of the dielectric. Subsequent layers are produced similarly before assembly into the final semiconductor package.
Copper plating methods must meet the stringent requirements of the semiconductor industry. For example, Cu deposits must be uniform and capable of flawlessly filling the small interconnect features of the device, for example, with openings of 100 nm or smaller.
Electrolytic Cu systems have been developed which rely on so-called “superfilling” or “bottom-up growth” to deposit Cu into high aspect ratio features. Superfilling involves filling a feature from the bottom up, rather than at an equal rate on all its surfaces, to avoid seams and pinching off that can result in voiding. Systems consisting of a suppressor and an accelerator as additives have been developed for superfilling. As the result of momentum of bottom-up growth, the Cu deposit is thicker on the areas of interconnect features than on the field area that does not have features. These overgrowth regions are commonly called overplating, mounding, bumps, or humps. Smaller features generate higher overplating humps due to faster superfill speed. The overplating poses challenges for later chemical and mechanical polishing processes that planarize the Cu surface. A third organic additive called a “leveler” is typically used to reduce the overgrowth.
As chip architecture gets smaller, with interconnects having openings on the order of 100 nm and smaller through which Cu must grow to fill the interconnects, there is a need for enhanced bottom-up speed. That is, the Cu must fill “faster” in the sense that the rate of growth on the feature bottom must be substantially greater than the rate of growth on the rest of areas, and even more so than in conventional superfilling of larger interconnects.
In addition to superfilling and overplating issues, micro-defects may form when electrodepositing Cu for filling interconnect features. One defect that can occur is the formation of internal voids inside the features. As Cu is deposited on the feature side walls and top entry of the feature, deposition on the side walls and entrance to the feature can pinch off and thereby close access to the depths of the feature especially with features which are small (e.g., <100 nm) and/or which have a high aspect ratio (depth:width) if the bottom-up growth rate is not fast enough. Smaller feature size or higher aspect ratio generally requires faster bottom-up speed to avoid pinching off. Moreover, smaller size or higher aspect ratio features tend to have thinner seed coverage on the sidewall and bottom of a via/trench where voids can also be produced due to insufficient copper growth in these areas. An internal void can interfere with electrical connectivity through the feature.
Microvoids are another type of defect which can form during or after electrolytic Cu deposition due to uneven Cu growth or grain recrystallization that happens after Cu plating.
In a different aspect, some local areas of a semiconductor substrate, typically areas where there is a Cu seed layer deposited by physical vapor deposition, may not grow Cu during the electrolytic deposition, resulting in pits or missing metal defects. These Cu voids are considered to be “killer defects,” as they reduce the yield of semiconductor manufacturing products. Multiple mechanisms contribute to the formation of these Cu voids, including the semiconductor substrate itself. However, Cu electroplating chemistry has influence on the occurrence and population of these defects.
Other defects are surface protrusions, which are isolated deposition peaks occurring at localized high current density sites, localized impurity sites, or otherwise. Copper plating chemistry has influence on the occurrence of such protrusion defects. Although not considered as defects, Cu surface roughness is also important for semiconductor wafer manufacturing. Generally, a bright Cu surface is desired as it can reduce the swirl patterns formed during wafer entry in the plating solution. Roughness of Cu deposits makes it more difficult to detect defects by inspection, as defects may be concealed by peaks and valleys of rough surface topography. Moreover, smooth growth of Cu is becoming more important for flawlessly filling of fine interconnect structures as the roughness can cause pinch off of feature and thereby close access to the depths of the feature. It is generally recognized that Cu plating chemistry, including suppressor, accelerator, and leveler, has great influence on the roughness of Cu deposits.